1. Field of the Invention
The present invention relates to a memory device comprising an array of memory cells, and to a method of controlling leakage current within such a memory device.
2. Description of the Prior Art
When developing memory devices, significant development effort is expended in seeking to improve the performance, and/or reduce the power consumption, associated with write and read operations. For example, the articles “A Step-Down Boosted-Wordline Scheme for 1-V Battery-Operated Fast SRAMs”, by H Morimura et al, IEEE Journal of Solid-State Circuits, Volume 33, No. 8, August 1998, Pages 1220 to 1227, “PVT-and-Aging Adaptive Wordline Boosting for 8T SRAM Power Reduction” by A Raychowdhury et al, ISSCC 2010, Session 19, High-Performance Embedded Memory, 19.6, Pages 352 to 354, and “Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation” by M Iijima et al, Journal of Computers, Volume 3, No. 5, May 2008, Pages 34 to 40, describe various techniques for boosting a word line voltage for either performance or power reduction reasons.
The article “A 45 nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage” by D Wang et al, IEEE 2007, Pages 211 to 214 describes write and read enhancement mechanisms which boost the ground line to a negative potential. As another approach for improving performance, the article “An 8T Sub-Threshold SRAM Cell Utilising Reverse Short Channel Effect for Write Margin and Read Performance Improvement” by T Hyoung Kim et al, IEEE 2007 Custom Integrated Circuits Conference (CICC), Pages 241 to 244, describes improving write margin and read performance of 8T sub-threshold SRAMs by using long channel devices to utilise the pronounced reverse short channel effect. The article “8T Single-Ended Sub-Threshold SRAM with Cross-Point Data-Aware Write Operation” by Yi Chiu et al, IEEE 2011, pages 169 to 174, describes a 8T SRAM cell suitable for low power and low voltage operation, the cell having a structure which maintains disturbance free read operation, whilst improving the write-ability of the cell in order to improve the minimum voltage at which write operations can be performed.
Whilst articles such as those mentioned above are concerned with improving performance and/or reducing power consumption of the memory device, another issue is becoming more and more significant, this issue being the amount of leakage current observed within the memory device.
As process geometries shrink in modern data processing systems, the variability in the operating characteristics of the individual circuit elements increases. Considering as an example a memory device consisting of an array of memory cells, it will be understood that each memory cell will typically consist of a number of electronic components such as transistors, and the variability in those individual components significantly increases as process geometries shrink. Furthermore, there is an increasing desire to operate data processing systems at lower and lower supply voltages, but as the supply voltage decreases, reliability issues due to the variations in the individual components become more prominent.
One reliability concern arises from the fact that leakage current can increase within the individual memory cells as the process geometries shrink. There are various potential leakage current paths within a memory device, but one area of concern is leakage current arising through components connected to a bit line within the memory device.
An array of memory cells will typically be arranged as a plurality of rows and columns, each row of memory cells being coupled to at least one associated word line (in some implementations there will be separate word lines for write operations and read operations), and each column of memory cells forming at least one column group. One or more bit lines will typically be associated with each column group (again some implementations will provide separate write bit lines and read bit lines), and each memory cell in the column group will have components coupled to such bit lines.
When the memory cells in one or more columns are not being accessed, there will continue to be various components coupled to the bit lines, and these can give rise to leakage paths through which leakage current occurs, increasing the power consumption of the device.
Considering as an example a single-ended memory cell, such a memory cell uses a single read bit line coupled via coupling circuitry to an internal node of the memory cell to allow the data value stored in that memory cell to be read during a read operation. The single read bit line is precharged to a first voltage level (typically the supply voltage Vdd) prior to a read operation, and then if a memory cell coupled to that read bit line is addressed during a read operation (by an asserted read word line signal on the read word line to which that memory cell is coupled), the voltage on the bit line will either stay at the first voltage level, or will discharge towards a second voltage level (typically a ground potential), depending on the value stored within the memory cell.
When the memory cells of a column group are not being subjected to a read operation, all of the memory cells within a column group will still be coupled to the read bit line via their associated coupling circuitry, and this can give rise to significant leakage current.
Accordingly, it would be desirable to provide an improved technique for reducing such leakage current within a memory device, without compromising performance of the memory device.